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wireless components tv mixer-oscillator-pll tua 6010xs version 1.0 specification august 1999 preliminary
edition 03.99 published by infineon technologies ag i. gr., sc, balanstra?e 73, 81541 mnchen ? infineon technologies ag i. gr. 24.08.99. all rights reserved. attention please! as far as patents or other rights of third parties are concerned, liability is only assumed for components, not for application s, processes and circuits im- plemented within components or assemblies. the information describes the type of component and shall not be considered as assured characteristics. terms of delivery and rights to change design reserved. due to technical requirements components may contain dangerous substances. for information on the types in question please cont act your nearest infineon technologies office. infineon technologies ag is an approved cecc manufacturer. packing please use the recycling operators known to you. we can also help you C get in touch with your nearest sales office. by agreeme nt we will take packing material back, if it is sorted. you must bear the costs of transport. for packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for an y costs incurred. components used in life-support devices or systems must be expressly authorized for such purpose! critical components 1 of the infineon technologies ag, may only be used in life-support devices or systems 2 with the express written approval of the infineon technologies ag. 1 a critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life- support device or system, or to affect its safety or effectiveness of that device or system. 2 life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sust ain human life. if they fail, it is reasonable to assume that the health of the user may be endangered. abm ? , aop ? , arcofi ? , arcofi ? -ba, arcofi ? -sp, digitape ? , epic ? -1, epic ? -s, elic ? , falc ? 54, falc ? 56, falc ? -e1, falc ? -lh, idec ? , iom ? , iom ? -1, iom ? -2, ipat ? -2, isac ? -p, isac ? -s, isac ? -s te, isac ? -p te, itac ? , iwe ? , musac ? -a, octat ? -p, quat ? -s, sicat ? , sicofi ? , sicofi ? - 2, sicofi ? -4, sicofi ? -4c, slicofi ? are registered trademarks of infineon technologies ag. ace ? , asm ? , asp ? , potswire ? , quadfalc ? , scout ? are trademarks of infineon technologies ag. revision history: current version: 08.99 previous version:data sheet page (in previous version) page (in current version) subjects (major changes since last revision)
product info product info wireless components specification, august 1999 package tua 6010xs preliminary product info general description the tua 6010xs device combines a digitally programmable phase locked loop (pll), with a mixer-oscillator block including two balanced mixers and oscillators for use in tv tuners. features n pll with short lock-in time; no asynchronous divider stage n fast i 2 c bus mode possible n 4 programmable chip addresses n short pull-in time for quick channel access and optimized loop stability n 3 high-current switch outputs n 2 ttl inputs n 5-level a/d converter n lock-in flag n power-down flag n few external components n frequency and amplitude-stable balanced oscillator for the vhf, hyper and uhf frequency range n optimum decoupling of input frequency from oscillator n double balanced mixer with wide dynamic range and low-impedance inputs for the vhf, hyper and uhf frequency range n internal band switch n internal low-noise reference volt- age source n package tssop 28 n full esd protection application n the ic is suitable for all tuners in tv- and vcr-sets or cable set-top receivers for analog tv an d igital vi deo b roadcasting. ordering information type ordering code package tua 6010 xs q67007-a5211 p-tssop-28-1
1 table of contents 1 table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 2 product description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.1 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.3 application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.4 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.1 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.2 pin definition and function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.4 circuit description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3.4.1 mixer-oscillator block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3.4.2 pll block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3.4.3 i2c-bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 4 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.1 application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.2 hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 5 reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.1 electrical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.1.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.1.2 operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 5.1.3 ac/dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 5.2 bit allocation read / write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 5.3 i2c bus timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 5.4 test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
2 product description 2.1 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.3 application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.4 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 contents of this chapter
product description 2 - 2 tua 6010xs preliminary wireless components specification, august 1999 2.1 overview the tua 6010xs device combines a digitally programmable phase locked loop (pll), with a mixer-oscillator block including two balanced mixers and oscilla- tors for use in tv tuners. the pll block with four hard-switched chip addresses forms a digitally pro- grammable phase locked loop. with a 4 mhz quartz crystal, the pll permits precise setting of the frequency of the tuner oscillator up to 900 mhz in incre- ments of 62.5 khz. the tuning process is controlled by a microprocessor via an i 2 c bus. the device has three output ports, which all can also be used as input ports (two ttl inputs and one a/d converter input). a flag is set when the loop is locked. the input ports and lock flag can be read by the processor via the i 2 c bus. the mixer-oscillator block includes two balanced mixers (double balanced mixer with low-impedance input), two frequency and amplitude-stable balanced oscillators for vhf, hyper and uhf, a low-noise reference voltage source and a band switch. 2.2 features n pll with short lock-in time; no asynchronous divider stage n fast i 2 c bus mode possible n 4 programmable chip addresses n short pull-in time for quick channel access and optimized loop stability n 3 high-current switch outputs n 2 ttl inputs n 5-level a/d converter n lock-in flag n power-down flag n few external components n frequency and amplitude-stable balanced oscillator for the vhf, hyper and uhf frequency range n optimum decoupling of input frequency from oscillator n double balanced mixer with wide dynamic range and low-impedance inputs for the vhf, hyper and uhf frequency range n internal band switch n internal low-noise reference voltage source n package tssop 28 n full esd protection
product description 2 - 3 tua 6010xs preliminary wireless components specification, august 1999 2.3 application n the ic is suitable for all tuners in tv- and vcr-sets or cable set-top receivers for analog tv an d igital vi deo b roadcasting. 2.4 package outlines p-tssop-28-1
3 functional description 3.1 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.2 pin definition and function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.4 circuit description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 contents of this chapter
functional description 3 - 2 tua 6010xs preliminary wireless components specification, august 1999 3.1 pin configuration pin_config.wmf figure 3-1 pin configuration ou-b2 ou-c1 ou-c2 ou-b1 ov-b2 ov-c1 ov-c2 ov-b1 gnd a tune chgpmp p0 / i0 p1 / i1 p2 / adc mixu mixux mixv mixvx v vcca cas ifout ifoutx gnd d sda scl v vccd q qx 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 tua 6010xs
functional description 3 - 3 tua 6010xs preliminary wireless components specification, august 1999 3.2 pin definition and function table 3-1 pin definition and function pin no. symbol function 1 2 mixu mixux uhf mixer input, low-impedance, symmetri- cal to mixux uhf mixer input, low-impedance, symmetri- cal to mixu 3 4 mixv mixvx vhf or hyper mixer input, low-imped- ance, symmetrical to mixvx vhf or hyper mixer input, low-imped- ance, symmetrical to mixv 5 v vcca positive supply voltage for analog block 6 cas chip address select 7 8 ifout ifoutx open collector mixer output, high-imped- ance, symmetrical to ifoutx inverse open collector mixer output, high- impedance, symmetrical to ifout 9 gnd d digital ground 12 34 6 87
functional description 3 - 4 tua 6010xs preliminary wireless components specification, august 1999 10 sda data input/output for the i 2 c bus 11 scl clock input for the i 2 c bus 12 v vccd positive supply voltage for digital block (pll) 13 14 q qx 4 mhz low-impedance crystal oscillator input inverse 4 mhz low-impedance crystal oscil- lator input 15 p2/adc port output / adc input 16 p1/i1 port output / ttl input 10 11 13 14 15 16
functional description 3 - 5 tua 6010xs preliminary wireless components specification, august 1999 17 p0/i0 port output / ttl input 18 19 chgpmp tune charge pump output / loop filter vco tuning voltage output 20 gnd a analog ground 21 22 23 24 ov-b1 ov-c2 ov-c1 ov-b2 vhf oscillator amplifier, high-impedance base input, symmetrical to ov-b2 vhf oscillator amplifier, high-impedance collector output, symmetrical to ov-c1 vhf oscillator amplifier, high-impedance collector output, symmetrical to ov-c2 vhf oscillator amplifier, high-impedance base input, symmetrical to ov-b1 17 18 19 21 22 23 24
functional description 3 - 6 tua 6010xs preliminary wireless components specification, august 1999 25 26 27 28 ou-b1 ou-c2 ou-c1 ou-b2 uhf oscillator amplifier, high-impedance base input, symmetrical to ou-b2 uhf oscillator amplifier, high-impedance collector output, symmetrical to ou-c1 uhf oscillator amplifier, high-impedance collector output, symmetrical to ou-c2 uhf oscillator amplifier, high-impedance base input, symmetrical to ou-b1 25 26 27 28
functional description 3 - 7 tua 6010xs preliminary wireless components specification, august 1999 3.3 block diagram figure 3-2 block diagram vco vcox crystal oscillator isolation amplifier oscillator uhf ov-b2 ov-c1 ov-c2 ov-b1 ou-b2 ou-c1 ou-c2 28 27 26 25 24 23 22 mixer uhf mixer vhf hyp 12345678 121314 mixv mixvx mixu mixux v vcca cas ifout ifoutx gnd d qx q v/u 9 v vccd 10 11 sda scl i2c-bus interface i/o-ports phase- det.& chgpmp ou-b1 gnd a tune chgpmp p0/io p1/ i1 p2/adc 21 20 19 18 17 16 15 ref.- divider progr. divider cy f ref isolation amplifier oscillator uhf oscillator vhf/hyp
functional description 3 - 8 tua 6010xs preliminary wireless components specification, august 1999 3.4 circuit description 3.4.1 mixer-oscillator block the mixer oscillator section includes two balanced mixers (double balanced mixer), two balanced oscillators for vhf and/or hyper and uhf, a reference voltage source and a band switch. filters between tuner input and ic separate the tv frequency signals into two bands. the band switch ensures that only one mixer-oscillator block at a time is activated. in the activated band the signal passes a frontend stage with mos- fet amplifier, a double-tuned bandpass filter and is then fed to the balanced mixer input of the ic which has a low-impedance input. the input signal is mixed there with the on chip oscillator signal from the acti- vated oscillator section. 3.4.2 pll block the mixer-oscillator signal vco/vcox is internally dc-coupled as a differential signal at the programmable divider inputs. the signal subsequently passes through a programmable divider with ratio n = 256 through 32767 and is then compared in a digital frequency / phase detector to a reference frequency f ref = 62.5 khz. this frequency is derived from a balanced, low-impedance 4 mhz crystal oscil- lator (pin q, qx) divided by q = 64. the phase detector has two outputs up and down that drive two current sources i+ and i- of a charge pump. if the negative edge of the divided vco sig- nal appears prior to the negative edge of the reference signal, the i+ current source pulses for the duration of the phase difference. in the reverse case the i- current source pulses. if the two signals are in phase, the charge pump output (chgpmp) goes into the high-impedance state (pll is locked). an active low- pass filter integrates the current pulses to generate the tuning voltage for the vco (internal amplifier, external pullup resistor at tune and external rc cir- cuitry). the charge pump output is also switched into the high-impedance state when the control bit t0 = 1. here it should be noted, however, that the tuning voltage can alter over a long period in the high-impedance state as a result of self-discharge in the peripheral circuity. tune may be switched off by the con- trol bit os to allow external adjustments. when the vco is not working the pll locks to a tuning voltage of 33v. by means of control bit 5i the pump current can be switched between two val- ues by software. this programmability permits alteration of the control response of the pll in the locked-in state. in this way different vco gains can be com- pensated, for example.
functional description 3 - 9 tua 6010xs preliminary wireless components specification, august 1999 the software-switched ports p0, p1, p2 are general-purpose open-collector outputs. the test bit t1 = 1, switches the test signals f ref (4 mhz / 64) and c y (divided input signal) to p0 and p1 respectively. p0, p1, p2 are bidirectional. the lock detector resets the lock flag fl when the width of the charge pump cur- rent pulses is greater than the period of the crystal oscillator (i.e. 250 ns). hence, when fl = 1, the maximum deviation of the input frequency from the programmed frequency is given by d f = i p (k vco / f q ) (c 1 +c 2 ) / (c 1 c 2 ) where i p is the charge pump current, k vco the vco gain, f q the crystal oscilla- tor frequency and c 1 , c 2 the capacitances in the loop filter (see application cir- cuit). as the charge pump pulses at 62.5 khz (= f ref ), it takes a maximum of 16 m s for fl to be reset after the loop has lost lock state. once fl has been reset, it is set only if the charge pump pulse width is less than 250 ns for eight consecutive f ref periods. therefore it takes between 128 and 144 m s for fl to be set after the loop regains lock. 3.4.3 i 2 c-bus interface data is exchanged between the processor and the pll via the i 2 c bus. the clock is generated by the processor (input scl), while pin sda functions as an input or output depending on the direction of the data (open collector, external pull-up resistor). both inputs have hysteresis and a low-pass characteristic, which enhance the noise immunity of the i 2 c bus. the data from the processor pass through an i 2 c bus controller. depending on their function the data are subsequently stored in registers. if the bus is free, both lines will be in the marking state (sda, scl are high). each telegram begins with the start condition and ends with the stop condition. start condition: sda goes low, while scl remains high. stop condition: sda goes high while scl remains high. all further information transfer takes place during scl = low, and the data is forwarded to the control logic on the positive clock edge. the table 1 bit allocation should be referred to the following description. all telegrams are transmitted byte-by-byte, followed by a ninth clock pulse, during which the control logic returns the sda line to low (acknowledge condition). the first byte is comprised of seven address bits. these are used by the pro- cessor to select the pll from several peripheral components (chip select). the lsb bit (r/w) determines whether data are written into (r/w = 0) or read from (r/w = 1) the pll. in the data portion of the telegram during a write operation, the msb bit of the first or third data byte determines whether a divider ratio or control information is to follow. in each case the second byte of the same data type has to follow the first byte. if the address byte indicates a read operation, the pll generates an acknowl- edge and then shifts out the status byte onto the sda line. if the processor gen- erates an acknowledge, a further status byte is output; otherwise the data line
functional description 3 - 10 tua 6010xs preliminary wireless components specification, august 1999 is released to allow the processor to generate a stop condition. the status word consists of two bits from the ttl input ports, three bits from the a/d converter, the lock flag and the power-on flag. four different chip addresses can be set by appropriate connection of pin cas (see table 2 address selection). when the supply voltage is applied, a power-on reset circuit prevents the pll from setting the sda line to low, which would block the bus. the power-on reset flag por is set at power-on and when v vccd goes below 3.2 v. it will be reset at the end of a read operation.
4 applications 4.1 application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.2 hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 contents of this chapter
applications 4 - 2 tua 6010xs preliminary wireless components specification, august 1999 4.1 application circuit figure 4-1 evaluation board 2.2p 6 6 15 16 17 18 19 20 21 22 23 24 25 26 27 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 4 1 3 3 1 4 1n 22p 22p 1n 2.7p 2.7p 2.2p 2.2p 1.2p 1.2p 1.2p 1.2p tua 6010xs uhf vhf v vcca if output scl sda v vccd 27p 4.7n 18p +33v 4.7n 47p 4.7p 22n 100k 1k 33k 4.7n 4.7k 1k 4.7n ba 592 bb639c 1k 1k 82p 2.2p 100p 2.2k 2.2k 3.3k 4.7n 22k 220 220 cas 4.7n 100p 4.7n 4.7n 47 12p 4.7n 4.7p 470p bb639c 100p 4mhz 1:1 *) 1:1 *) *) toko b4f type 617db-1023
applications 4 - 3 tua 6010xs preliminary wireless components specification, august 1999 4.2 hints see separate available application note tua 6010xs .
5 reference 5.1 electrical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.1.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.1.2 operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 5.1.3 ac/dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 5.2 bit allocation read / write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 5.3 i2c bus timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 5.4 test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 contents of this chapter
reference 5 - 2 tua 6010xs preliminary wireless components specification, august 1999 5.1 electrical data 5.1.1 absolute maximum ratings warning the maximum ratings may not be exceeded under any circumstances, not even momentarily and individually, as permanent damage to the ic will result. table 5-1 absolute maximum ratings, ambient temperature t amb =-20c ... + 80c parameter symbol limit values unit remarks min max pll supply voltage v vccd -0.3 +6 v chgpmp v chgpmp i chgpmp -0.3 1 v ma crystal oscillator pins q, qx v q i q -5 v vccd v ma bus input/output sda bus output current sda v sda i sda(l) -0.3 +6 5 v ma bus input scl v scl -0.3 +6 v port outputs p0, p1, p2 v p -0.3 +13 v chip address switch cas v cas -0.3 v vccd v vco tuning output (loop filter) v tune -0.3 +35 v bus output sda i sdal -1 5 ma open collector port outputs p0, p1, p2 i p(l) -1 15 ma open collector total port output current s i p(l) 20 ma t max = 0,1 sec. at 6 v junction temperature t j +125 c storage temperature t stg -40 +125 c thermal resistance (junction to ambient) r thsa 130 k/w
reference 5 - 3 tua 6010xs preliminary wireless components specification, august 1999 5.1.2 operating range within the operational range the ic operates as described in the circuit description. the ac / dc characteristic limits are not guaranteed. table 5-1 absolute maximum ratings, ambient temperature t amb =-20c ... + 80c (continued) parameter symbol limit values unit remarks min max mixer-oscillator supply voltage v vcca -0.3 +6 v mix inputs vhf/uhf v mix v/u i mix v/u -5 2 6 v ma vco base voltage v ou-b/ov-b -0.3 3 v vco collector voltage v ou-c/ov-c v vcca v if output v ifout v ifoutx 6 v all values are referred to ground (pin), unless stated otherwise. currents with a positive sign flows into the pin and currents with a negative sign flows out of pin. esd-protection * all pins unless otherwise specified v esd -1 1 kv mixer inputs mixu / mixv v esd mix -500 500 v pin 1, 2, 3, 4 mixer outputs ifout / ifoutx v esd if -500 500 v pin 7, 8 ports v esd p -500 500 v pin 15, 16, 17 charge pump v esd cp -500 500 v pin 18 *according to mil std 883d, method 3015.7 and eos/esd assn. standard s5.1 - 1993 table 5-2 operating range parameter symbol limit values unit test conditions l item min max supply voltage v vccd +4.5 +5.5 v supply voltage v vcca +4.5 +5.5 v mixer output voltage v ifout v ifoutx +4.5 +5.5 v open collector programmable divider factor n256 32767 vhf mixer input frequency range f mixv 30 500 mhz uhf mixer input frequency range f mixu 400 900 mhz vhf oscillator frequency range f ov 30 500 mhz uhf oscillator frequency range f ou 400 900 mhz ambient temperature t amb -20 +80 c
reference 5 - 4 tua 6010xs preliminary wireless components specification, august 1999 5.1.3 ac/dc characteristics table 5-3 ac/dc characteristics with t amb 25 c, v vcca = 5 v, v vccd = 5 v symbol limit values unit test conditions l item min typ max digital unit pll 1.1 supply current i vccd 19 24 29 ma v vccd = 5 v crystal oscillator connections q, qx crystal frequency f q 3.2 4.0 4.8 mhz series resonance crystal resistance r q 10 100 w series resonance oscillation frequency f q 3,99975 4,000 4,00025 mhz f q = 4 mhz input impedance z q -600 -750 -900 w f q = 4 mhz margin from 1st (fundamental) to 2nd and 3rd harmonics a h 20 db f q = 4 mhz charge pump output chgpmp high output current i cph 90 220 300 m a 5i = 1, v cp = 2 v low output current i cpl 22 50 75 m a 5i = 0, v cp = 2 v tristate current i cpz +1 na t0 = 1, v cp = 2 v output voltage v cp 1.0 2.5 v locked drive output tune (open collector) high output current i th 10 m av th = 33 v, t0 = 1 low output voltage v tl 0.5 vi tl = 1.0 ma i 2 c-bus 1.2 bus inputs scl, sda high input voltage v ih 3 5.5 v low input voltage v il 0 1.5 v high input current i ih 10 m av ih = v s low input current i il -10 m av il = 0 v bus output sda (open collector) high output current i oh 10 m av oh = 5.5 v low output voltage v ol 0.4 vi ol = 3 ma edge speed scl,sda rise time t r 300 ns fall time t f 300 ns
reference 5 - 5 tua 6010xs preliminary wireless components specification, august 1999 table 5-3 ac/dc characteristics with t amb 25 c, v vcca = 5 v, v vccd = 5 v (continued) symbol limit values unit test conditions l item min typ max clock timing scl frequency f scl 0 400 khz high pulse width t h 0.6 m s low pulse width t l 1.3 m s start condition set-up time t susta 0.6 m s hold time t hsta 0.6 m s stop condition set up time t susto 0.6 m s bus free t buf 1.3 m s data transfer set-up time t sudat 0.1 m s hold time t hdat 0 m s input hysteresis scl, sda (1) v hys 200 mv pulse width of spikes which are suppressed t sp 0 50 ns capacitive load for each bus line c l 400 pf port outputs p0, p1, p2 (open collector) high output current i poh 1 m av poh = 5 v low output voltage v pol 0.5 vi pol = 15 ma ttl port inputs p0, p1 high input voltage v pih 2.7 v low input voltage v pil 0.8 v high input current i pih 10 m av pih = 13.5 v low input current i pil -10 m av pil = 0 v adc port input p2 high input current i adch 10 m a low input current i adcl -10 m a address selection input cas high input current i cash 50 m av cash = 5 v low input current i casl -50 m av casl = 0 v
reference 5 - 6 tua 6010xs preliminary wireless components specification, august 1999 table 5-3 ac/dc characteristics with t amb 25 c, v vcca = 5 v, v vccd = 5 v (continued) symbol limit values unit test conditions l item min typ max analog unit mixer-oscillator 2.1 current consumption i vcca 11 15 19 ma bit v/u = low i vcca 14 18 22 ma bit v/u = high mixer current i if-v/if-u 4 68 ma mixer output impedance r ifout,if outx 20 k w parallel equivalent circuit, f if = 38,9 mhz c ifout,if outx 0.5 pf parallel equivalent circuit, f if = 38,9 mhz vhf and hyper band section 2.2 oscillator frequency range f oscv 80 170 mhz v d = 0,5..28 v; vhf f osch 140 450 mhz v d = 0,5..28 v; hyp oscillator drift d f oscv 400 khz v s = 5 v 10% d f oscv 500 khz d t = 25 c d f oscv 100 khz t = 5 s up to 15 min after switching on oscillator pulling v mixv 100 108 db m v d f = 10 khz in channel e2 v mixv 100 108 db m v d f = 10 khz in channel s10 v mixv 80 88 db m v d f int = e2 + n + 5 - 1 mhz v mixv 80 88 db m v d f int = s10 + n + 5 - 1 mhz oscillator phase noise l(fm) vh f -80 -86 dbc/ hz fm = 10 khz, application circuit mixer gain g mixv 11 14 17 db mixer noise figure f mixv 58 db channel e2 (dsb) f mixv 58 db channel 10 (dsb) crosstalk f in/lo v mixv 150 1000 mv rms max. input level for 10 db distance f in/lo
reference 5 - 7 tua 6010xs preliminary wireless components specification, august 1999 table 5-3 ac/dc characteristics with t amb 25 c, v vcca = 5 v, v vccd = 5 v (continued) symbol limit values unit test conditions l item min typ max mixer input impedance r mixv 20 w serial equivalent circuit, f mixv = 300 mhz l mixv 10 nh serial equivalent circuit, f mixv = 300 mhz if suppression a if 20 db v mixb = 80 db m v uhf section 2.3 oscillator frequency range f oscu 440 900 mhz v t = 0,5...28 v oscillator drift d f oscu 400 khz v s = 5 v 10% d f oscu 800 khz d t = 25 c d f oscu 100 khz t = 5 s up to 15 min after switching on oscillator pulling v mixu 100 108 db m v d f = 10 khz in channel e21 v mixu 100 108 db m v d f = 10 khz in channel e68 v mixu 80 88 db m v d f int = e21 + n + 5 - 1 mhz v mixu 80 88 db m v d f int = e68 + n + 5 - 1 mhz oscillator phase noise l(fm) uh f -80 -86 dbc/ hz fm = 10 khz, application circuit mixer gain g mixu 11 14 17 db mixer noise figure f mixu 69 db channel e21 (dsb) 710 db channel e68 (dsb) crosstalk f in/lo v mixu 150 1000 mv rms max. input level for 10 db distance f in/lo mixer input impedance r mixu 20 w serial equivalent circuit, f mixu = 600 mhz l mixu 10 nh serial equivalent circuit, f mixu = 600 mhz if suppression a if 20 db v mixb = 80 db m v n this value is only guaranteed in lab.
reference 5 - 8 tua 6010xs preliminary wireless components specification, august 1999 5.2 bit allocation read / write *) msb shifted first. divider ratio: n = 16384 x n14 + 8192 x n13 + 4096 x n12 + 2048 x n11 + 1024 x n10 + 512 x n9 + 256 x n8 +128 x n7 + 64 x n6 + 32 x n5 + 16 x n4 + 8 x n3 + 4 x n2 + 2 x n1 + n0 control bytes: n ports p0, p1, p2: p0...p2=1 open-collector output is active p0...p2=0 open-collector output is inactive, ttl-inputs i1, i0 and adc available n bandswitch v/u: v/u=1 switch to osc/mix uhf v/u=0 switch to osc/mix vhf n pump current 5i: 5i=1 high pd output current 5i=0 low pd output current n disabling tuning voltage os: os=1 disables tune os=0 enables tune table 5-4 byte msb*) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb ack remarks write data address byte 11 00 0ma1 ma0 0 a progr. divider byte 1 0 n14 n13 n12 n11 n10 n9 n8 a progr. divider byte 2 n7 n6 n5 n4 n3 n2 n1 n0 a control byte 1 15i t1 t0 11 1os a control byte 2 v/u x xx xp2 p1 p0 a read data address byte 11 00 0ma1 ma0 1 a status byte por fl xi1 i0 a2 a1 a0 a
reference 5 - 9 tua 6010xs preliminary wireless components specification, august 1999 status byte: n power on reset flag por: flag is set at power-on and reset at the end of read operation n pll lock flag fl: flag is set to 1 when loop is locked n ttl-inputs i1, i0: input data from pins p1/i1, p0/i0 n adc bits a2,a1,a0: digital outputs of the 5-level adc table 5-5 address selection voltage at cas ma1 ma0 (0...0.1) * v vcc 00 open circuit 01 (0.4...0.6) * v vcc 10 (0.9...1) * v vcc 11 table 5-6 test modes test mode t1 t0 normal operation 00 p1 = cy output, p0 = f ref output 10 charge pump output, chgpmp is in high-impedance state 01 ttl-inputs i1/i0 are cy/f ref inputs of phase detector 11 table 5-7 a/d converter levels voltage at p2 / adc a2 a1 a0 (0...0.15) * v vcc 00 0 (0.15...0.3) * v vcc 00 1 (0.3...0.45) * v vcc 01 0 (0.45...0.6) * v vcc 01 1 (0.6...1) * v vcc 10 0
reference 5 - 10 tua 6010xs preliminary wireless components specification, august 1999 5.3 i 2 c bus timing diagram note: sda scl ack. ack. 2nd byte 1st byte 3rd byte ack. ack. addressing ma r/w ma telegram examples: start-addr-dr1-dr2-cw1-cw2-stop start = start condition start-addr-cw1-cw2-dr1-dr2-stop addr = address byte start-addr-dr1-dr2-stop dr1 = prog. divider byte 1 start-addr-cw1-cw2-stop dr2 = prog. divider byte 2 cw1 = control byte 1 cw2 = control byte 2 stop = stop condition 4th byte
reference 5 - 11 tua 6010xs preliminary wireless components specification, august 1999 5.4 test circuits figure 5-1 dc and rf parameter measurement 10 15 16 17 18 19 20 21 22 23 24 25 26 27 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 4.7p 470p 1 5 1 4 2 4 2 5 1n 22p 22p 1n 2.2p 2.2p 2.2p 2.2p 1.2p 1.2p 1.2p 1.2p tua 6010xs smt4 1:1 smt4 1:1 uhf vhf v vcca if output scl sda v vccd 22p 4.7n 18p +33v 4.7n 22p 5.6p 56n 100k 1k 39k 470n 1k 1k 1n ba 592 bb639c 33k 33k 82p 2.2p 100p 33k 33k bb639c 3.3k 10n 12k 100 100 cas 470n 100p 33p 1n 100p 1n
reference 5 - 12 tua 6010xs preliminary wireless components specification, august 1999 figure 5-2 measurement of crystal oscillator frequency 4 mhz i vcc 5v p0 18 pf counter tua 6010xs gnd d v vcc 5 k q f ref test mode: t1 = high t0 = low f q = f ref * 64 p1 counter f vco = f cy * n n: divider ratio f cy 5 k

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